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Espressif Systems /ESP32-S2 /UART0 /IDLE_CONF

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Interpret as IDLE_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RX_IDLE_THRHD0TX_IDLE_NUM0TX_BRK_NUM

Description

Frame end idle time configuration

Fields

RX_IDLE_THRHD

A frame end signal is generated when the receiver takes more time to receive one byte data than this register’s value, in the unit of bit time (the time it takes to transfer one bit).
TX_IDLE_NUM

This register is used to configure the duration time between transfers, in the unit of bit time (the time it takes to transfer one bit).
TX_BRK_NUM

This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when UART_TXD_BRK is set to 1.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data